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1 ltc4230 4230f n allows safe board insertion and removal from a live backplane n controls three supply voltages from 1.7v to 16.5v with v cc1 3 v cc2 3 v cc3 n programmable soft-start with inrush current limiting, no external gate capacitor required n faster turn-off time with no gate capacitor n dual level overcurrent fault protection n programmable overcurrent response time n programmable overvoltage protection n automatic retry or latched mode operation n independent n-channel fet high side drivers n user-programmable supply voltage power-up rate n fb n pin monitors v out n and signals reset n n glitch filter eliminates spurious reset n signals the ltc ? 4230 is a 3-channel hot swap tm controller that allows a board to be safely inserted and removed from a live backplane. internal high side switch drivers control the gates of external n-channel mosfets for supply voltages ranging from 1.7v to 16.5v. the ltc4230 pro- vides soft-start and inrush current limiting during the programmable start-up period. on-chip current limit comparators provide dual level circuit breaker protection. the slow comparators trip at v cc n C 50mv and activate in 10 m s or are programmed by an external filter capacitor. the fast comparators trip at v cc n C 150mv and typically respond in 500ns. each fb n pin monitors its own output supply voltage and signals its reset pin. the on pin turns the chip on and off and can be used for a reset function. the ltc4230 also provides additional functions including fault indication, autoretry or latchoff modes, programmable current limit response time based on the fault and filter pins functionality. n electronic circuit breaker n hot board insertion and removal (either on backplane or on removable card) n industrial high side switch/circuit breaker triple hot swap controller with multifunction current control , ltc and lt are registered trademarks of linear technology corporation. 3-channel hot swap controller hot swap is a trademark of linear technology corporation. r sense2 0.007 cx2 100nf cx1 100nf rx2 10 q2 irf7413 v cc1 on fault gnd ltc4230 15 67 8161718543 fb3 1 13 14 12 11 sense 1 gate 1 v cc2 sense 2 gate 2 sense 3 gate 3 v cc3 reset 3 2 r sense3 0.007 rx1 10 r8 5.1k r9 12k q3 irf7413 v out1 3.3v 5a v out2 2.5v 5a v out3 1.8v 5a r sense1 0.007 cx3 100nf rx3 10 c timer * 0.1 f c filter ** 15pf q1 irf7413 z3*** z2*** z1*** * system on time: 6.2ms **circuit breaker response time: 19.5 s ***optional z1, z2, z3: smaj10 reset 2 19 fb2 20 r7 10k reset 1 9 fb1 10 r10 11k r11 12k r6 10k r12 18k r13 12k 4230 ta01 r5 10k pcb edge connector (male) backplane connector (female) v cc1 3.3v long v cc2 2.5v long v cc3 1.8v long short fault gnd long short r2 10k r1 10k pcb connection sense reset 3 timer filter reset 2 reset 1 applicatio s u features typical applicatio u descriptio u
2 ltc4230 4230f symbol parameter conditions min typ max units v cc supply voltage (v cc1 ) l 2.700 16.5 v supply voltage (v cc2 )v cc2 v cc1 l 2.375 16.5 v supply voltage (v cc3 )v cc3 (v cc1 C 1v) l 1.700 15.5 v i cc supply current (i cc1 ) on = v cc1 , fb1 = high l 1.8 3 ma supply current (i cc2 ) on = v cc1 , fb2 = high l 75 150 m a supply current (i cc3 ) on = v cc1 , fb3 = high l 65 150 m a v lko1 undervoltage lockout , channel 1 v cc1 low to high transition l 2.15 2.35 2.52 v v lko2 undervoltage lockout , channel 2 v cc2 low to high transition l 1.98 2.15 2.32 v v lko3 undervoltage lockout , channel 3 v cc3 low to high transition l 1.09 1.19 1.29 v v lkohst1 undervoltage lockout hysteresis, channel 1 100 mv v lkohst2 undervoltage lockout hysteresis, channel 2 45 mv v lkohst3 undervoltage lockout hysteresis, channel 3 35 mv i in, fb n fb n pin input current 0v v fb n v cc n l 0.1 10 m a i in, on on pin input current 0v v on v cc1 l 0.1 10 m a i in, sense n input current for sense n 0v v sense n v cc n l 0.1 15 m a v cb(fast) circuit breaker n trip voltage fast comparator l 135 150 165 mv v cb(slow) slow comparator l 40 50 60 mv i gate n , up gate n pull-up current charge pump on, 0 v gate n < 0.2v l C12.5 C10 C6.5 m a i gate n , dn normal gate n pull-down current on low, v gate n = 5v 200 m a fast gate n pull-down curent fault latched and circuit breaker 16 ma tripped or in uvlo, v gate n = 5v i leak reset n leakage current v reset n = 15v, pull-down device off l 0.1 2.5 m a t jmax = 125 c, q ja = 95 c/ w order part number supply voltage (v cc n ) ............................................. 17v sense n pins ............................... C 0.3v to (v cc + 0.3v) fb n , on pins ............................... C 0.3v to (v cc + 0.3v) timer pin ...................................................C 0.3v to 2v gate n pins ........................... internally limited (note 3) reset n , fault, filter pins ....................C 0.3v to 17v operating temperature range ltc4230c ............................................... 0 c to 70 c ltc4230i ............................................ C 40 c to 85 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec).................. 300 c ltc4230cgn ltc4230ign absolute axi u rati gs w ww u package/order i for atio uu w (note 1) the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc1 = 3.3v, v cc2 = 2.5v,v cc3 = 1.8v unless otherwise noted. (note 2) electrical characteristics consult ltc marketing for parts specified with wider operating temperature ranges. 1 2 3 4 5 6 7 8 9 10 top view gn package 20-lead plastic ssop 20 19 18 17 16 15 14 13 12 11 fb3 reset 3 gate 3 sense 3 v cc3 v cc1 sense 1 gate 1 reset 1 fb1 fb2 reset 2 gate 2 sense 2 v cc2 on gnd fault timer filter
3 ltc4230 4230f the l denotes specifications which apply over the full operating temperature range, otherwise specifications are t a = 25 c. v cc1 = 3.3v, v cc2 = 2.5v,v cc3 = 1.8v unless otherwise noted. (note 2) electrical characteristics d v gate n external n-channel gate drive v gate1, 2 C v cc1, 2 (for v cc1, 2 = 2.7v, v cc3 = v cc1 C 1v) l 4.5 8 v v gate3 C v cc3 (for v cc1, 2 = 2.7v, v cc3 = v cc1 C 1v) l 5.5 9 v v gate1, 2 C v cc1, 2 (for v cc1, 2 = 3.3v, v cc3 = v cc1 C 1v) l 510v v gate3 C v cc3 (for v cc1, 2 = 3.3v, v cc3 = v cc1 C 1v) l 611v v gate n C v cc n (for v cc1, 2 = 5v, v cc3 = v cc1 C 1v) l 916v v gate n C v cc n (for v cc1, 2 = 12v or 15v, l 718v v cc3 = v cc1 C 1v) v gate n , 0v gate n overvoltage lockout 0.25 v threshold v fb n fb n low threshold voltage fb n high to low transition l 1.209 1.234 1.259 v d v fb n fb n line regulation 2.7v v cc1 16.5v 0.5 mv v fb n , hst fb n hysteresis 3mv v onhi on high threshold voltage on low to high transition l 1.250 1.314 1.380 v v onlo on low threshold voltage on high to low transition l 1.172 1.234 1.270 v v onhst on hysteresis 80 mv i filter filter pull-up current during slow fault condition l C 2.5 C 2 C1.3 m a filter pull-down current during normal and reset conditions l 71013 m a v filter filter threshold latched off threshold, filter low to high l 1.10 1.26 1.42 v v filterhst filter threshold hysteresis C70 mv i tmr timer pull-up current timer on l C23 C20 C17 m a timer pull-down current timer off, v fault = low l 0.9 1.6 2.3 m a v timer = 1.5v 2.5 ma v tmr timer threshold timer low to high l 1.172 1.234 1.27 v timer high to low l 0.3 0.5 v v fault fault low threshold voltage fault high to low l 1.172 1.234 1.27 v v fault, hst fault hysteresis fault low to high 50 mv i fault, up fault pull-up current l C 2.5 C 2 C 1.5 m a v olfault output low voltage i fault = 1.6ma, v cc1 = 5v l 0.19 0.4 v v olreset n output low voltage i reset n = 1.6ma, v cc1 = 5v l 0.19 0.4 v t gatefc fast comp n trip to v cb = 0mv to 200mv step l 0.5 1 m s gate n discharging t faultsc slow comparator trip to v cb = 0mv to 100mv step, filter floating 10 m s filter high and fault latched 10nf at filter pin to gnd l 712 ms t ovpftr filter comparator trip to v filter = 0v to 5v l 812 m s gate n discharging t extfault fault low to gate discharging v fault = 5v to 0v l 1.5 3 4.5 m s t reset circuit breaker reset time on held low to guarantee fault high l 15 30 m s t off turn-off time on goes low to gate n off 8 m s symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: all current into device pins is positive; all current out of device pins is negative; all voltages are referenced to ground unless otherwise specified. note 3: an internal zener at the gate n pin clamps the charge pump voltage to a typical maximum operating voltage of 26v. external overdrive of the gate n pin beyond the internal zener voltage may damage the part. the gate n capacitance must be < 0.15 m f at maximum v cc . if a lower gate n pin voltage is desired, use an external zener diode.
4 ltc4230 4230f typical perfor a ce characteristics uw v cc1 supply voltage (v) 2 4 6 8 10 12 14 16 18 supply current (ma) 4230 g01 8 7 6 5 4 3 2 1 0 v cc2 = 2.5v v cc3 = 1.8v ?0 c 25 c 85 c supply voltage (v) 2 4 6 8 10 12 14 16 18 supply current (ma) 4230 g02 0.6 0.5 0.4 0.3 0.2 0.1 0 ?0 c 25 c 85 c channel 3 channel 2 temperature ( c) ?5 undervoltage lockout threshold voltage (v) 125 4230 g03 ?5 25 75 50 150 0 50 100 2.5 2.2 1.9 1.6 1.3 1.0 v cc3 high v cc1 high v cc1 low v cc2 high v cc2 low v cc3 low temperature ( c) ?5 fb n pin input current (na) 125 4230 g04 ?5 25 75 50 150 0 50 100 5 4 3 2 1 0 v fb n = 5v temperature ( c) ?5 on pin input current (na) 125 4230 g05 ?5 25 75 50 150 0 50 100 6 5 4 3 2 1 0 v on = 5v temperature ( c) ?5 sense n input current (na) 125 4230 g06 ?5 25 75 50 150 0 50 100 100 90 80 70 60 50 40 30 20 10 0 v sense n = 5v temperature ( c) ?5 on threshold voltage (v) 125 4230 g07 ?5 25 75 50 150 0 50 100 1.36 1.34 1.32 1.30 1.28 1.26 1.24 1.22 v cc1 = 3.3v v cc2 = 2.5v v cc3 = 1.8v on pin high on pin low v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fast comparator trip voltage (mv) 4230 g08 152.0 151.5 151.0 150.5 150.0 149.5 149.0 148.5 148.0 ?0 c 25 c 85 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 slow comparator trip voltage (mv) 4230 g09 52.0 51.5 51.0 50.5 50.0 49.5 49.0 ?0 c 25 c 85 c channel 1 supply current vs v cc1 supply voltage fb n pin input current vs temperature on threshold vs temperature channels 2 and 3 supply current vs supply voltage uvlo threshold voltage vs temperature on pin input current vs temperature sense n input current vs temperature fast comparator threshold vs v cc1 supply voltage slow comparator threshold vs v cc1 supply voltage
5 ltc4230 4230f typical perfor a ce characteristics uw v cc1 supply voltage (v) 2 4 6 8 10 12 14 16 18 gate pull-down current ( a) 4230 g10 280 260 240 220 200 180 160 140 120 v cc2 = 2.5v v cc3 = 1.8v v gate n = 2.5v ?0 c 25 c 85 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fast pull-down current (ma) 4230 g11 20 18 16 14 12 10 v cc2 = 2.5v v cc3 = 1.8v v gate n = 5v ?0 c 25 c 85 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 i gate current ( a) 4230 g12 12 11 10 9 8 7 6 ?0 c 25 c 85 c v cc1 supply voltage (v) 2 4 6 8 10 12 14 16 18 ? v gate voltage (v) 4230 g13 16 14 12 10 8 6 4 2 0 v cc2 = v cc1 v cc3 = v cc1 ?1v v gate1 = v gate2 v gate3 temperature ( c) ?5 v gate ?v cc1 voltage (v) 125 4230 g14 ?5 25 75 50 150 0 50 100 16 14 12 10 8 6 4 v cc1 = 15v v cc1 = 5v v cc1 = 12v v cc1 = 3.3v v cc1 = 2.7v temperature ( c) ?5 gate overvoltage lockout threshold (v) 125 4230 g15 ?5 25 75 50 150 0 50 100 0.5 0.4 0.3 0.2 0.1 0 v cc1 = 3.3v v cc2 = 2.5v v cc3 = 1.8v v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 4230 g16 0.5 0.4 0.3 0.2 0.1 0 gate overvoltage lockout threshold (v) v cc2 = 2.5v v cc3 = 1.8v temperature ( c) ?5 v fb threshold voltage (v) 125 4230 g17 ?5 25 75 50 150 0 50 100 1.239 1.238 1.237 1.236 1.235 1.234 1.233 1.232 v fb n high v fb n low v cc1 = 3.3v v cc2 = 2.5v v cc3 = 1.8v v cc1 supply voltage (v) fb threshold voltage (v) 4230 g18 1.238 1.237 1.236 1.235 1.234 1.233 0 2 4 6 8 10 12 14 16 18 fb high fb low normal gate n pull-down current vs v cc1 supply voltage v gate n C v cc n vs v cc1 supply voltage gate n overvoltage lockout threshold vs v cc1 supply voltage fast gate n pull-down current vs v cc1 supply voltage gate n output source current (pull-up) vs v cc1 supply voltage v gate1 C v cc1 vs temperature gate n overvoltage lockout threshold vs temperature v fb n threshold voltage vs temperature v fb n threshold voltage vs v cc1 supply voltage
6 ltc4230 4230f typical perfor a ce characteristics uw temperature ( c) ?5 i filter current low ( a) 125 4230 g19 ?5 25 75 50 150 0 50 100 1.6 1.8 2.0 2.2 2.4 2.6 v cc1 = 3.3v v cc1 = 2.7v v cc1 = 5v v cc1 = 16.5v v cc1 = 12v v cc2 = 2.5v v cc3 = 1.8v temperature ( c) ?5 i filter current ( a) 125 4230 g20 ?5 25 75 50 150 0 50 100 12.0 11.2 10.4 9.6 8.8 8.0 v cc2 = 2.5v v cc3 = 1.8v v cc1 = 16.5v v cc1 = 12v v cc1 = 5v v cc1 = 2.7v v cc1 = 3.3v temperature ( c) ?5 i filter threshold voltage (v) 125 4230 g21 ?5 25 75 50 150 0 50 100 1.30 1.28 1.26 1.24 1.22 1.20 1.18 1.16 1.14 v cc2 = 2.5v v cc3 = 1.8v v cc1 = 16.5v v cc1 = 12v v cc1 = 5v v cc1 = 2.7v v cc1 = 3.3v v cc1 = 16.5v v cc1 = 3.3v v cc1 = 12v v cc1 = 2.7v i filter low i filter high v cc1 = 5v v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fault threshold voltage (v) 4230 g22 1.29 1.28 1.27 1.26 1.25 1.24 1.23 ?0 c ?0 c 25 c 85 c 85 c high threshold low threshold 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fault pull-up current ( a) 4230 g23 2.5 2.3 2.1 1.9 1.7 1.5 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 timer pull-up current ( a) 4230 g24 23 22 21 20 19 18 17 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 timer pull-down current ( a) 4230 g25 2.0 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 timer pull-down current (ma) 4230 g26 9 8 7 6 5 4 3 2 1 0 ?0 c v timer = 1.5v 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 timer high threshold (v) 4230 g27 1.237 1.236 1.235 1.234 1.233 1.232 1.231 1.230 ?0 c 85 c 25 c filter pull-up current vs temperature fault threshold voltage vs v cc1 supply voltage timer pull-down current (after second cycle) vs v cc1 supply voltage filter pull-down current vs temperature filter threshold voltage vs temperature timer pull-up current (during first cycle) vs v cc1 supply voltage timer fast pull-down (end of the first cycle) current vs v cc1 supply voltage timer high threshold vs v cc1 supply voltage fault pull-up current vs v cc1 supply voltage
7 ltc4230 4230f typical perfor a ce characteristics uw v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 timer low threshold (v) 4230 g28 0.32 0.31 0.30 0.29 0.28 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 v ol voltage (v) 4230 g29 0.25 0.20 0.15 0.10 0.05 0 temperature ( c) v ol voltage (v) 4230 g30 0.25 0.22 0.19 0.16 0.13 0.10 75 125 ?5 25 75 50 150 0 50 100 v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fast comparator response time ( s) 4230 g31 650 600 550 500 450 400 350 300 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 slow comparator response time ( s) 4230 g32 14 13 12 11 10 9 8 7 6 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 filter comparator response time ( s) 4230 g33 10 9 8 7 6 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 fault low to gate n discharging ( s) 4230 g34 5 4 3 2 1 0 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 circuit breaker reset time ( s) 4230 g35 20 18 16 14 12 10 ?0 c 85 c 25 c v cc1 supply voltage (v) 0 2 4 6 8 10 12 14 16 18 turn-off time ( s) 4230 g36 11 10 9 8 7 6 5 ?0 c 85 c 25 c timer low threshold vs v cc1 supply voltage fast comparator response time vs v cc1 supply voltage fault low to gate n discharging vs v cc1 supply voltage v ol (reset n , fault) vs v cc1 supply voltage slow comparator response time (filter floating) vs v cc1 supply voltage filter comparator response time vs v cc1 supply voltage circuit breaker reset time vs v cc1 supply voltage turn-off time vs v cc1 supply voltage v ol (reset n , fault) vs temperture
8 ltc4230 4230f fb3 (pin 1): the fb3 (feedback) pin is an input to the fbcomp3 comparator which monitors the v cc3 output supply voltage through an external resistor divider. if v fb3 < 1.234v, reset 3 pin pulls low. an internal glitch filter at fbcomp3s output prevents triggering a reset condition due to negative voltage transients. if v fb3 > 1.237v, reset 3 pin goes high after exiting undervoltage lockout. reset 3 (pin 2): an open-drain n-channel device whose source connects to gnd (pin 14). this pin pulls low if the voltage at fb3 (pin 1) falls below the fb3 threshold (1.234v). this pin requires an external pull-up resistor to v out3 . if an undervoltage lockout condition occurs, reset 3 pulls low independently of fb3 to prevent false glitches. gate 3 (pin 3): the output signal at this pin is the high side gate drive for channel 3s external n-channel mosfet pass transistor. an internal charge pump produces a 4.5v (minimum) to 18v (maximum) gate drive voltage for v cc1 supply voltages from 2.7v to 16.5v, respectively. as shown in the block diagram for each channel, an internal charge pump supplies a 10 m a gate current and sufficient gate voltage drive to the external mosfet. the internal charge pump produces a minimum 4.5v gate drive for v cc1 < 4.75v. for v cc1 > 4.75v, the minimum gate voltage drive is 9v. for v cc1 3 12v, the minimum gate voltage drive is 7v which is set by an internal zener diode clamp connected between the gate 3 pin and gnd. sense 3 (pin 4): circuit breaker sense pin for channel 3. with a sense resistor placed in the power path between v cc3 and sense 3, channel 3s electronic circuit breaker trips if the voltage across the sense resistor (v cc3 C v sense3 ) exceeds the thresholds set internally for slow comp3 and fast comp3, as shown in the block diagram. the threshold for slow comp3 is v cb(slow) = 50mv, and the electronic circuit breaker trips if the voltage across r sense3 exceeds 50mv for 10 m s, or for the time delay programmed by c filter . to adjust slow comp3s delay, please refer to the section on adjusting slow comp n s response time. under transient conditions where large step current changes can and do occur over shorter periods of time, a pi fu ctio s uuu second (fast) comparator instead trips the electronic circuit breaker. the threshold for fast comp3 is set at v cb(fast) = 150mv, and the circuit breaker trips if the voltage across the r sense3 exceeds 150mv for more than 500ns. fast comp3s delay is fixed in the ltc4230 and cannot be adjusted. to disable channel 3s electronic circuit breaker, connect the v cc3 and sense 3 pins together. v cc3 (pin 5): positive supply input for channel 3. v cc3 operates from 1.7v to 15.5v (v cc3 v cc1 C 1v) and its supply current, i cc3 , is typically 65 m a. the master uvlo circuit disables all three gate n outputs of the ltc4230 until the voltage at v cc3 exceeds 1.19v. v cc1 (pin 6): this is the positive supply input to the ltc4230, the power supply input for channel 1, and the power supply input for all three internal charge pumps. the ltc4230 operates from 2.7v to 16.5v, and the i cc1 supply current is typically 1.8ma. the master uvlo circuit disables all three gate n outputs of the ltc4230 if v cc1 is less than 2.35v. the internal charge pump outputs are enabled when v cc1 > 2.35v, v cc2 > 2.15v, and v cc3 > 1.19v. sense 1 (pin 7): circuit breaker sense pin for channel 1. with a sense resistor placed in the power path between v cc1 and sense 1, channel 1s electronic circuit breaker trips if the voltage across the sense resistor (v cc1 C v sense1 ) exceeds the thresholds set internally for slow comp1 and fast comp1, as shown in the block diagram. the threshold for slow comp1 is v cb(slow) = 50mv, and the electronic circuit breaker trips if the voltage across r sense1 exceeds 50mv for 10 m s, or for the time delay programmed by c filter . to adjust slow comp1s delay, please refer to the section on adjusting slow comp n s response time. under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. the threshold for fast comp1 is set at v cb(fast) = 150mv, and the circuit breaker trips if the voltage across the r sense1 exceeds 150mv for more than 500ns. fast comp1s delay is fixed in the ltc4230 and cannot be adjusted. to disable channel 1s electronic circuit breaker, connect the v cc1 and sense 1 pins together.
9 ltc4230 4230f pi fu ctio s uuu gate 1 (pin 8): the output signal at this pin is the high side gate drive for channel 1s external n-channel fet pass transistor. an internal charge pump produces a 4.5v (minimum) to 18v (maximum) gate drive voltage for supplies in the range of 2.7v v cc1 16.5v, respectively. as shown in the block diagram, each channels internal charge pump is powered by v cc1 and supplies a 10 m a gate current and sufficient gate voltage drive to the external fet. the internal charge pump produces a minimum 4.5v gate voltage drive for v cc1 < 4.75v. for v cc1 > 4.75v, the minimum gate voltage drive is 9v. for v cc1 3 12v, the minimum gate voltage drive is 7v which is set by an internal zener diode clamp connected between the gate 1 pin and gnd. reset 1 (pin 9): an open-drain n-channel device whose source connects to gnd (pin 14). this pin pulls low if the voltage at fb1 (pin 10) falls below the fb1 threshold (1.234v). during the start-up cycle, reset 1 goes high impedance at the end of the second timing cycle after fb1 goes above the fb1 threshold. this pin requires an exter- nal pull-up resistor to v out1 . if an undervoltage lockout condition occurs, reset 1 pulls low independently of fb1 to prevent false glitches. fb1 (pin 10): the fb1 (feedback) pin is an input to the fbcomp1 comparator which monitors the v cc1 output supply voltage through an external resistor divider. if v fb1 < 1.234v, reset 1 pin pulls low. an internal glitch filter at fbcomp3s output prevents triggering a reset condition due to negative voltage transients. if v fb1 > 1.237v after the second timing cycle, reset 1 goes high. filter (pin 11): overcurrent fault timing pin and over- voltage fault set pin. with a capacitor connected from this pin to ground, the response time of all three slow comp comparators can be adjusted. note that the response time of the slow comp comparators cannot be adjusted individually. timer (pin 12): a capacitor connected from this pin to gnd sets the ltc4230s system timing. the ltc4230s initial and second start-up timing cycles and its discharge mode delay time are controlled by this capacitor. fault (pin 13): fault is a dual function (an input and an output) internal to the ltc4230. connected to this pin are an analog comparator (comp6) and an open-drain n-channel fet. during normal operation, if comp6 is driven below 1.234v, all electronic circuit breakers trip and each gate pin pulls low. referring to the block diagram, fault incorporates an internal 2 m a current source pull up. this allows the ltc4230 to begin a second timing cycle (v fault > 1.284v) and start up properly. this also allows the use of the fault pin as a status output. under normal operating conditions, the fault output is a logic high. two conditions cause an active low on fault: 1) the ltc4230s electronic circuit breakers trip because of an output short circuit (v out n = 0v) or because of a fast output overcurrent transient (fast comp n trips its circuit breaker); or 2) v filter > 1.26v. the fault output is driven to logic low and is latched logic low until the on pin is driven to logic low for 30 m s (the t reset duration). gnd (pin 14): device ground connection. connect this pin to the systems analog ground plane. on (pin 15): an active high signal used to enable or disable ltc4230 operation. as shown in the ltc4230 block diagram, comp1s threshold is set at 1.234v and its hysteresis is set at 80mv. if a logic high signal is applied to the on pin (v on > 1.314v), the first timing cycle begins if an overvoltage condition does not exist on any of the gate n pins (pins 3, 8, and 18). if a logic low signal is applied to the on pin (v on < 1.234v), each gate n pin is pulled low by an internal, dedicated 200 m a current sink. the on pin can also be used to reset all three electronic circuit breakers. if the on pin is cycled low for more than 1 t reset n (max) period and then high following a circuit breaker trip, all internal circuit breakers are reset and the ltc4230 begins a new start-up cycle. v cc2 (pin 16): positive supply input for channel 2. v cc2 operates from 2.375v to 16.5v and its supply current, i cc2 , is typically 75 m a. the master uvlo circuit disables all three gate n outputs of the ltc4230 until the voltage at v cc2 exceeds 2.15v.
10 ltc4230 4230f sense 2 (pin 17): circuit breaker sense pin for chan- nel 2. with a sense resistor placed in the power path between v cc2 and sense 2, channel 2s electronic circuit breaker trips if the voltage across the sense resistor (v cc2 C v sense2 ) exceeds the thresholds set internally for slow comp2 and fast comp2, as shown in the block diagram. the threshold for slow comp2 is v cb(slow) = 50mv and the electronic circuit breaker trips if the voltage across r sense2 exceeds 50mv for 10 m s, or for the time delay programmed by c filter . to adjust slow comp2s delay, please refer to the section on adjusting slow comp n s response time. under transient conditions where large step current changes can and do occur over shorter periods of time, a second (fast) comparator instead trips the electronic circuit breaker. the threshold for fast comp2 is set at v cb(fast) = 150mv, and the circuit breaker trips if the voltage across the r sense2 exceeds 150mv for more than 500ns. fast comp2s delay is fixed in the ltc4230 and cannot be adjusted. to disable channel 2s electronic circuit breaker, connect the v cc2 and sense 2 pins together. gate 2 (pin 18): the output signal at this pin is the high side gate drive for channel 2s external n-channel fet pass transistor. an internal charge pump produces a 4.5v (minimum) to 18v (maximum) gate drive voltage for v cc1 supply voltages from 2.7v to 16.5v, respectively. as shown in the block diagram for each channel, an internal charge pump supplies a 10 m a gate current and sufficient gate voltage drive to the external fet. the internal charge pump produces a minimum 4.5v gate drive for v cc1 < 4.75v. for v cc1 > 4.75v, the minimum gate voltage drive is 9v. for v cc1 3 12v, the minimum gate voltage drive is 7v which is set by an internal zener diode clamp connected between the gate 2 pin and gnd. reset 2 (pin 19): an open-drain n-channel device whose source connects to gnd (pin 14). this pin pulls low if the voltage at fb2 (pin 20) falls below the fb2 threshold (1.234v). this pin requires an external pull-up resistor to v out2 . if an undervoltage lockout condition occurs, the reset 2 pin pulls low independently of fb2 to prevent false glitches. fb2 (pin 20): the fb2 (feedback) pin is an input to the fbcomp2 comparator which monitors the v cc2 output supply voltage through an external resistor divider. if v fb2 < 1.234v, reset 2 pulls low. an internal glitch filter at fbcomp3s output prevents triggering a reset condition due to negative voltage transients. if v fb2 > 1.237v, reset 2 pin goes high after exiting undervoltage lockout. pi fu ctio s uuu
11 ltc4230 4230f block diagra w + tmrbuffer 1.234v + channel 2 control channel two fast comp2 v cc2 150mv fasthi + + fbcomp2 1.234v 0.25v power bad + gatelo comparator v clamp2 = v cc2 + 12v gatelo fpd 200 a mg2 + slow comp2 v cc2 cpo2 50mv slowhi cur_limit + glitch filter fpd 10 a channel three (duplicate of channel two) + channel 1 control channel one fast comp1 v cc1 150mv fasthi + + fbcomp1 1.234v 0.25v power bad mr2 mr1 + gatelo comparator v clamp1 = v cc1 + 12v gatelo fpd 200 a mg1 + slow comp1 v cc1 cpo1 50mv slowhi cur_limit + glitch filter on 10 a v cc1 2 a v cc1 2 a system control + comp1 v cc1 on comparator 1.234v fault m2 m4 m5 + fault comparator comp6 1.234v faultlo delay charge pump 3 v cc1 charge pump 2 v cc1 cpo3 v cc3 v cc2 v cc1 uvlo 0.25v 1.234v ref cpo2 cpo1 charge pump 1 osc + filter comparator ftr_charge 1.26v ftrhi 0.3v 1.234v + tmrlo comparator tmrlo tmrhi + tmrhi comparator 10 a v cc1 20 a m6 fault 1.6 a 19 reset 2 20 fb2 17 sense 2 16 v cc2 2 reset 3 1 fb3 4 sense 3 5 v cc3 9 reset 1 10 fb1 7 sense 1 fault 6 v cc1 13 11 15 filter on 18 gate 2 3 gate 3 8 gate 1 gnd 14 timer 12 mf2 mf1
12 ltc4230 4230f hot circuit insertion when circuit boards are inserted into or removed from live backplanes, the supply bypass capacitors can draw huge transient currents from the backplane power bus as they charge. the transient currents can cause permanent dam- age to the connector pins as well as cause glitches on the system supply, causing other boards in the system to reset. the ltc4230 is designed to turn a printed circuit boards supply voltages on and off in a controlled manner, allow- ing the circuit board to be safely inserted or removed from a live backplane. the device provides a system reset signal to indicate when board supply voltage drops below a pre- determined level, as well as a dual function fault monitor. output voltage monitor the ltc4230 uses a 1.234v bandgap reference, precision voltage comparators and external resistor dividers to monitor the output supply voltages as shown in figure 1. the operation of the supply monitor in normal mode is il- lustrated in figure 2. reset 1 pulls low during an undervoltage lockout condition. it remains low until the end of the soft-start cycle (second timing cycle). fb1 then assumes control of reset 1 status. reset 2 and reset 3 also pull low during undervoltage lockout. however, fb2 controls reset 2 and fb3 controls reset 3 status imme- diately after clearing uvlo (figure 2, time points 5 and 6). if the voltage at fb n drops below its reset threshold (1.234v), the fbcomp comparator output pulls high. after passing through a glitch filter, reset n changes state. if the voltage at fb n increases above its reset threshold, the fbcomp comparator output changes state and reset n pulls high. + sense n r sense r2 r1 r3 10k v cc n v out gate n ltc4230 15 fb n mr n gnd on 4230 f01 reset n c timer 12 timer 14 c load q1 logic timer 1.234v reference fbcomp n m p reset 4 3 2 1 short long v cc on/reset gnd long pcb edge connector (male) backplane connector (female) + figure 1. supply voltage monitor block diagram applicatio s i for atio wu u u
13 ltc4230 4230f 1 2 5 6 3 4 second timing cycle (soft-start cycle) first timing cycle 1.234v 20 a pull-up 20 a pull-up 4230 f02 check for filter low (< v ref ) check for fault high (> v ref + 50mv) fast comparator armed out of uvlo v cc n , on uvlo (internal signal) timer v out1 v out2, 3 reset 1 reset 2, reset 3 gate n gate n < 0.25v 10 a pull-up slow comparator armed normal mode (v fb1 > 1.237v) (v fb2 , v fb3 > 1.237v) figure 2. supply monitor waveforms in normal mode applicatio s i for atio wu u u
14 ltc4230 4230f internal undervoltage lockout (uvlo) the ltc4230s power-on reset circuit initializes the start- up condition and ensures the chip is in the proper state if the input supply voltages are too low. if any one of the input supply voltages falls below its corresponding uvlo lower threshold (e.g., v cc1 < 2.25v, v cc2 < 2.105v or v cc3 < 1.155v), the ltc4230 enters uvlo mode and all three gate n pins are each pulled low by internal 200 m a current sinks. since the ltc4230s uvlo circuits have hysteresis, the device restarts when all three supply voltages rise above their corresponding uvlo high threshold (e.g., v cc1 > 2.35v, v cc2 > 2.15v and v cc3 > 1.19v) and the on pin goes high. in addition, users can utilize the on comparator (comp1) or the fault comparator (comp6) to effectively program a higher undervoltage lockout level. if the fault com- parator is used for this purpose, the system will wait for the input voltage to increase above the level set by the user before starting the second timing cycle. also, if the input voltage drops below the set level in normal operating mode, the user must cycle the on pin or v cc1 to restart the system. glitch filter for reset n each ltc4230 feedback comparator has a glitch filter to prevent reset n from generating a system reset if there are transients on the fb n pin. the relationship between glitch filter time and the feedback transient voltage is shown in figure 3. system timing system timing for the ltc4230 is generated in the equiva- lent circuit shown in figure 4. if the ltc4230s internal timing circuit is off, an internal n-channel fet connects the timer pin to gnd. if the timing circuit is enabled, an internal 20 m a current source is then connected to the timer pin to charge c timer at a rate given by equation 1: c charge -up rate timer = m 20 a c timer (1) when the timer pin voltage reaches tmrhis threshold of 1.234v, the timer pin is reset to gnd. equation 2 gives an expression for the timer period: tv c a timer timer = m 1 234 20 . (2) as a design aid, the ltc4230?s timer period as a function of the c timer using standard values from 0.1 m f to 10 m f is shown in table 1. feedback transient (mv) 0 glitch filter time ( s) 150 200 250 160 4211 f03 100 50 0 40 80 120 20 180 60 100 140 200 t a = 25 c figure 3. fb comparator glitch filter time vs feedback transient voltage + + 0.3v 20 a t timer ltc4230* v cc1 v ref 1.234v tmrlo logic tmrhi timer c timer m6 normal 4230 f04 *additional details omitted for clarity figure 4. ltc4230 system timing block diagram applicatio s i for atio wu u u
15 ltc4230 4230f ensuring a proper start-up sequence is also dependent on selecting the most appropriate value for c timer for the application. long timing periods affect overall system start-up times. a timing period set too short and the system may never start up. a good starting point is to set c timer = 1 m f and then adjust its value accordingly for the application. operating sequence power-up, start-up check and plug-in timing cycle the sequence of operations for the ltc4230 is illustrated in the timing diagram of figure 5. when a pc board is first inserted into a live backplane, the ltc4230 first performs 1 3 6 7 4 5 first timing cycle 20 a pull-up 20 a pull-up 4230 f05 normal mode second timing cycle check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.2v fast comparator armed if on is low and v fb n < 1.234v, reset 1, reset 2 and reset 3 pull low, respectively on timer gate n v out n reset 1 reset 2, reset 3 10 a pull-up 200 a pull-down slow comparator armed 8 9 power good (v fb n > 1.237v) power bad (v fb n < 1.234v) 200 a pull-down figure 5. normal power-up sequence table 1. t timer vs c timer c timer t timer 0.1 m f 6.2ms 0.22 m f 13.6ms 0.33 m f 20.4ms 0.47 m f 29ms 0.68 m f 42ms 0.82 m f 50.6ms 1 m f 61.7ms 2.2 m f 136ms 3.3 m f 204ms 4.7 m f 290ms 6.8 m f 420ms 8.2 m f 506ms 10 m f 617ms applicatio s i for atio wu u u
16 ltc4230 4230f a start-up check to make sure the supply voltage is above its 2.3v uvlo threshold (see time point 1). if the input supply voltage is valid, the gate of the external pass transistor is pulled to ground by the internal 200 m a current source connected at the gate n pin. the timer pin is held low by an internal n-channel pull-down transistor (see m6, ltc4230 block diagram) and the filter pin voltage is pulled to ground by an internal 10 m a current source. once v cc n and on (the on pin is >1.314v) are valid, the ltc4230 checks to make sure that gate n is off (v gate n < 0.25v) at time point 2. an internal timing circuit is enabled and the timer pin voltage ramps up at the rate described by equation 1. at time point 3 (the timing period programmed by c timer ), the timer pin voltage equals v tmr (1.234v). next, the timer pin voltage ramps down to time point 4 where the ltc4230 performs two checks: (1) filter pin voltage is low (v filter < 1.19v) and (2) fault pin voltage is high (v fault > 1.284v). if both conditions are met, the ltc4230 begins a second timing (soft-start) cycle. second timing (soft-start) cycle at the beginning of the second timing cycle (time point 5), the ltc4230s fast comp n is armed and an internal 10 m a current source working with an internal charge pump provides the gate drive to the external pass transis- tor. an expression for the gate n voltage slew rate is given by equation 3: v slew rate dv dt a c gate gate gate n n n , = m 10 (3) where c gate n = power mosfet gate input capacitance (c iss ) for channel n . for example, a si4410dy (a 30v n-channel power mosfet) exhibits an approximate c gate of 3300pf at v gs = 10v. the ltc4230s gate n voltage rate-of-change (slew rate) for this example would be: v slew rate dv dt a pf v ms gate gate n n ,. = m = 10 3300 303 the inrush current being delivered to the load while the gate n is ramping is dependent on c load n and c gate n . equation 4 gives an expression for the inrush current during the second timing cycle: i dv dt ca c c inrush gate load load gate ==m n n n n 10 (4) for example, if c gate n = 3300pf and c load n = 2000 m f, the inrush current charging c load n is: ia f f a inrush =m m m = 10 2000 0 0033 606 . . (5) at time point 7, the output voltage trips fbcomp n s threshold, signaling an output voltage power good con- dition. reset 2 and reset 3 pull high. at time point 8, reset 1 asserts high, slow comp is armed and the ltc4230 enters a fault monitor mode. soft-start with current limiting during the second timing cycle, the inrush current is described by equation 4. note that there is a one-to-one correspondence in the inrush current to c load n . if the inrush current is large enough to cause a voltage drop greater than 50mv across the sense resistor, an internal servo loop controls the operation of the 10 m a current source at the gate n pin to regulate the load current to: i mv r limit softstart sense () n n = 50 (6) for example, the inrush current is limited to 5a when r sense n = 0.01 w . in this fashion, the inrush current is controlled and c load n is charged up slowly during the soft-start cycle. the timing diagram in figure 6 illustrates the operation of the ltc4230 in a normal power-up sequence with limited inrush current as described by equation 6. at time point 5, the gate pin voltage begins to ramp indicating that the power mosfet is beginning to charge c load n . at time point 5, the inrush current causes a 50mv voltage drop across r sense n and an internal servo loop engages, limit- ing the inrush current to a fixed level. at time point 6, the gate n pin voltage continues to ramp as c load n charges until v out n reaches its final value. the charging current applicatio s i for atio wu u u
17 ltc4230 4230f reduces, and the internal servo loop disengages. at the end of the soft-start cycle (time point 8), all reset n are high and all slow comp n are armed. power-off cycle as shown at time point 9, an external hard reset is initiated by pulling the on pin low (v on < 1.234v). all gate n pin voltages are ramped to ground by the internal 200 m a current sources, discharging c gate n and turning off the pass transistors. as c load n discharges, the output voltage crosses fbcomp n s threshold, signaling a power bad condition at time point 10. reset n then asserts low. 1 3 7 6 5 8 4 first timing cycle 20 a pull-up 20 a pull-up load current is regulating at 50mv/r sense n 4230 f06 normal mode second timing cycle check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.25v fast comparator armed if on is low and v fb n < 1.234v, reset 1, reset 2 and reset 3 pull low, respectively on timer gate n v out n i load n gate n v out n reset 1 reset 2, reset 3 10 a pull-up 200 a pull-down slow comparator armed 9 10 power good (v fb n > 1.237v) power bad (v fb n < 1.234v) 200 a pull-down figure 6. normal power-up sequence (with current limiting in second timing cycle) frequency compensation at soft-start if the external gate input capacitance (c iss ) is greater than 600pf, no external gate capacitor is required at gate n to stabilize the internal current-limiting loop during soft- start. otherwise, connect an external gate capacitor be- tween the gate n and gnd pins to increase the total gate capacitance above 600pf. the servo loop that controls the external mosfet during current limiting has a unity-gain frequency of about 105khz and phase margin of 80 for external mosfet gate input capacitances to 2.5nf. applicatio s i for atio wu u u
18 ltc4230 4230f using an external gate capacitor the ltc4230 automatically limits the inrush current in one of two ways: by controlling the gate n pin voltage slew rate or by actively limiting the inrush current. the ltc4230 uses gate n voltage slew rate limiting when c load n is small and/or the inrush current limit is set high. if gate n voltage slew rate control is preferred with large c load n , an external capacitor (c gx ) can be used from gate n to ground, as shown in figure 7. according to equation 3, adding c gx slows the gate n voltage slew rate at the expense of slower system turn-on and turn-off time. should this technique be used, values for c gx less than 150nf are recommended. electronic circuit breaker the ltc4230 features an electronic circuit breaker func- tion. it disconnects loads from power supplies when shorts or excessive load current conditions occur on any of the supplies and generates a fault signal. if a circuit breaker trips, its gate n pin is immediately pulled to ground, the external n-channel mosfet is quickly turned off and fault is latched low. the circuit breaker trips whenever the voltage across the sense resistor exceeds two different levels, each level set by the ltc4230s slow comp n and fast comp n (see block diagram). the slow comp n trips the circuit breaker if the voltage across the sense n resistor (v cc n C v sense n = v cb ) is greater than 50mv for 10 m s. there may be applications where this comparators re- sponse time is not long enough, for example, because of excessive supply voltage noise. to adjust the response time of the slow comp n , a capacitor is used at the ltc4230s filter pin (see section on adjusting slow comp n s response time). the fast comp n trips the circuit breaker to protect against fast load overcurrents if the transient voltage across the sense resistor is greater than 150mv for 500ns. the response time of the ltc4230s fast comp n is fixed. the timing diagram of figure 6 illustrates when the ltc4230s electronic circuit breaker is armed. after the first timing cycle, the ltc4230s fast comp n is armed at time point 5. arming fast comp n at time point 5 ensures that the system is protected against a short- circuit condition during the second timing cycle after c load n has been fully charged. at time point 8, slow comp n is armed when the internal control loop is disen- gaged. the timing diagrams in figures 8 and 9 illustrate the opera- tion of the ltc4230 when the load current conditions exceed the thresholds of the fast comp n (v cb(fast) > 150mv) and slow comp n (v cb(slow) > 50mv), respectively. 4 3 2 1 m1 si4410dy r sense 0.007 c gx * c load 4230 f07 + v cc n sense n ltc4230** gate n fb n r1 36k v out 5v 5a v in 5v r2 15k * ** values 150nf suggested additional details omitted for clarity = dv gate n dt v gate slew rate control 10 a c gate + c gx () figure 7. using an external capacitor at gate for gate voltage slew rate control and large c load an external gate capacitor may also be useful to decrease or eliminate current spikes through the mosfet when power is first applied. at power-up, the instantaneous in- put voltage step attempts to pull the mosfet gate up through the mosfets drain-to-gate capacitance. if the mosfets c iss is small, the gate can be pulled up high enough to turn on the mosfet, thereby allowing a current spike to the output. this event occurs during the time that the ltc4230 is coming out of uvlo and getting its intel- ligence to hold the gate pin low. an external capacitor attenuates the voltage to which the gate is pulled up and eliminates the current spike. the value required is depen- dent on the mosfet capacitance specifications. in typical applications, this capacitor is not required. applicatio s i for atio wu u u
19 ltc4230 4230f 1 3 6 5 7 4 20 a pull-up 20 a pull-up load current > 150mv/r sense n 4230 f08 check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.25v fast comparator armed slow comparator armed circuit breaker trips, all gate n pins pull low immediately on timer fault gate n gate n v out n v out n i out n filter 1.6 a pull-down 8 9 check for timer < 0.3v load current < 50mv/r sense n figure 8. output short circuit causes fast comparator to trip the circuit breaker applicatio s i for atio wu u u resetting the electronic circuit breaker once the ltc4230s circuit breaker is tripped, fault is asserted low and the gate n pin is pulled to ground. the ltc4230 remains latched off in this fault state until the external fault is cleared. to clear the internal fault detect circuitry and to restart the ltc4230, its on pin must be driven low (v on < 1.234v) for at least 30 m s, after which time fault goes high. toggling the on pin from low to high (v on > 1.314v) initiates a restart sequence in the ltc4230. the timing diagram in figure 10 illustrates a
20 ltc4230 4230f figure 9. output short-circuit causes slow comparator to trip circuit breaker 1 3 6 5 7 4 20 a pull-up 20 a pull-up 150mv/r sense n > load current > 50mv/r sense n 4230 f09 check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.25v fast comparator armed slow comparator armed circuit breaker trips, all gate n pins pull low immediately on timer fault gate n gate n v out n v out n i out n filter 1.6 a pull-down 10 a pull-down 1.26v 2 a pull-up 8 9 check for timer < 0.3v load current < 50mv/r sense n applicatio s i for atio wu u u
21 ltc4230 4230f 1 3 7 6 5 8 4 first timing cycle 4230 f10 second timing cycle discharging mode normal mode check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.25v fast comparator armed slow comparator armed once v filter > 1.26v, circuit breaker trips, all gate n pins pull low immediately 20 a pull-up 1.6 a pull-down 2 a pull-up v filter > 1.26v 10 a pull-down load current < 150mv/r sense n 20 a pull-up check for timer < 0.3v 9 10 on timer fault gate n v out n i load n filter gate n v out n load current is regulating at 50mv/r sense n figure 10. power-up into dead short in overcurrent condition applicatio s i for atio wu u u
22 ltc4230 4230f start-up sequence where the ltc4230 is powered up into a load overcurrent condition. note that the circuit breaker trips at time point 8 and is reset at time point 10. adjusting slow comp n s response time the response time of slow comp n is adjusted using a capacitor connected from the ltc4230s filter pin to ground. if this pin is left unused, slow comp n s delay defaults to 10 m s. during normal operation, the filter output pin is held low as an internal 10 m a pull-down current source is connected to this pin by transistor m4. this pull-down current source is turned off when an overcurrent load condition is detected by slow comp n . during an overcurrent condition, the internal 2 m a pull-up current source is connected to the filter pin by transis- tor m5, thereby charging c filter . as the charge on the capacitor accumulates, the voltage across c filter increases. once the filter pin voltage increases to 1.26v, the electronic circuit breaker trips and the ltc4230s gate n pins are switched quickly to ground by transistor mf n (refer to the block diagram). after the circuit breaker is tripped, m5 is turned off, m4 is turned on and the 10 m a pull-down current then holds the filter pin voltage low. slow comp n s response time from an overcurrent fault condition to when the circuit breaker trips (gate n off) is given by equation 7: tv c a s slowcomp filter n = m +m 126 2 10 . (7) for example, if c filter = 1000pf, slow comp n s response time = 640 m s. as a design aid, slow comp n s delay time (t slow comp ) versus c filter for standard values of c filter from 100pf to 1000pf is illustrated in table 2. table 2. t slowcomp n vs c filter c filter t slowcomp n 100pf 73 m s 220pf 149 m s 330pf 218 m s 470pf 306 m s 680pf 438 m s 820pf 527 m s 1000pf 640 m s sense resistor considerations the fault current level at which the ltc4230s internal electronic circuit breakers trip is determined by a sense resistor connected between the ltc4230s v cc n and sense n pins and two separate trip points. the first trip point is set by the slow comp n s threshold, v cb(slow) = 50mv, and the trip occurs if a load current fault condition exist for more than 10 m s. the current level at which the electronic circuit breaker trips is given by equation 8: i v r mv r trip slow cb slow sense sense () () n n nn == 50 (8) the second trip point is set by the fast comp n s thresh- old, v cb(fast) = 150mv, and occurs during fast load current transients that exist for 500ns or longer. the current level at which the circuit breaker trips in this case is given by equation 9: i v r mv r trip fast cb fast sense sense () () n n nn == 150 (9) as a design aid, the currents at which electronic circuit breaker trips for common values for r sense are shown in table 3. table 3. i trip(slow) and i trip(fast) vs r sense r sense i trip(slow) i trip(fast) 0.005 w 10a 30a 0.006 w 8.3a 25a 0.007 w 7.1a 21a 0.008 w 6.3a 19a 0.009 w 5.6a 17a 0.01 w 5a 15a for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc4230s v cc n and sense n pins are strongly recommended. the drawing in figure 11 illustrates the correct way of making connections between the ltc4230 and the sense resistor. pcb layout should be balanced and symmetrical to mini- mize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. applicatio s i for atio wu u u
23 ltc4230 4230f 4 3 2 1 + slow comp n v cc n v out n v cb n sense n r sense *additional details omitted for clarity 4230 f12 ltc4230* v cb(max) = 60mv v cb(nom) = 50mv v cb(min) = 40mv i load(max) v cc n 5v + figure 12. circuit breaker equivalent circuit for calculating r sense the power rating of the sense resistor should accommo- date steady-state fault current levels so that the compo- nent is not damaged before the circuit breaker trips. table 4 in the appendix lists suggested sense resistors that can be used with the ltc4230s circuit breaker. for example: if a sense resistor with 7m w 5% r tol is used for current limiting, the nominal trip current i trip(nom) = 7.1a. from equations 11 and 12, i trip(min) = 5.4a and i trip(max) = 9a respectively. for proper operation and to avoid the circuit breaker tripping unnecessarily, the minimum trip current (i trip(min) ) must exceed the circuits maximum operating load current. for reliability purposes, the operation at the maximum trip current (i trip(max) ) must be evaluated carefully. if necessary, two resistors with the same r tol can be connected in parallel to yield an r sense(nom) value that fits the circuit requirements. irc-tt sense resistor lr251201r010f or equivalent 0.01 , 1%, 1w current flow to load current flow to load to v cc n to sense n track width w: 0.03" per amp on 1 oz copper w 4230 f11 figure 11. making pcb connections to the sense resistor calculating circuit breaker trip current for a selected r sense value, the nominal load current that trips the circuit breaker is given by equation 10: i v r mv r trip nom cb nom sense nom sense nom () () () () == 50 (10) the minimum load current that trips the circuit breaker is given by equation 11. i v r mv r trip min cb min sense max sense max () () () () == 40 (11) where rr r sense max sense nom tol () () =+ ? ? ? ? ? ? 1 100 the maximum load current that trips the circuit breaker is given in equation 12. i v r mv r trip max cb max sense min sense min () () () () == 60 (12) where rr r sense min sense nom tol () ( ) = ? ? ? ? ? ? 1 100 power mosfet selection criteria to start the power mosfet selection process, choose the maximum drain-to-source voltage, v ds(max) , and the maximum drain current, i d(max) of the mosfet. the v ds(max) rating must exceed the maximum input supply voltage (including surges, spikes, ringing, etc.) and the i d(max) rating must exceed the maximum short-circuit current in the system during a fault condition. in addition, consider three other key parameters: 1) the required gate- source (v gs ) voltage drive, 2) the voltage drop across the drain-to-source on resistance, r ds(on) and 3) the maxi- mum junction temperature rating of the mosfet. power mosfets are classified into two categories: stan- dard mosfets (r ds(on) specified at v gs = 10v) and logic- level mosfets (r ds(on) specified at v gs = 5v). the absolute applicatio s i for atio wu u u
24 ltc4230 4230f maximum rating for v gs is typically 20v for standard mosfets. however, the v gs maximum rating for logic- level mosfets ranges from 8v to 20v depending upon the manufacturer and the specific part number. the ltc4230s gate overdrive as a function of v cc is illustrated in the typical performance curves. logic-level mosfets are recommended for low supply voltage applications and standard mosfets can be used for applications where supply voltage is greater than 4.75v. note that in some applications, the gate of the external mosfet can discharge faster than the output voltage when the circuit breaker is tripped. this causes a negative v gs voltage on the external mosfet. usually, the selected external mosfet should have a v gs(max) rating that is higher than the operating input supply voltage to ensure that the external mosfet is not destroyed by a negative v gs voltage. in addition, the v gs(max) rating of the mosfet must be higher than the gate overdrive voltage. lower v gs(max) rating mosfets can be used with the ltc4230 if the gate n overdrive is clamped to a lower voltage. the circuit in figure 13 illustrates the use of zener diodes to clamp the ltc4230s gate n overdrive signal if lower voltage mosfets are used. the r ds(on) of the external pass transistor should be low to make its drain-source voltage (v ds ) a small percentage of v cc . at a v cc = 2.5v, v ds + v rsense = 0.1v yields 4% error at the output voltage. this restricts the choice of mosfets to very low r ds(on) . at higher v cc voltages, the v ds requirement can be relaxed in which case mosfet package dissipation (p d and t j ) may limit the value of r ds(on) . table 5 lists some power mosfets that can be used with the ltc4230. power mosfet junction temperature is dependent on four parameters: current delivered to the load, i load , r ds(on) , junction-to-ambient thermal resistance, q ja , and the maxi- mum ambient temperature to which the circuit will be exposed, t a(max) . for reliable circuit operation, the maxi- mum junction temperature (t j(max) ) for a power mosfet should not exceed the manufacturers recommended value. this includes normal mode operation, start-up, current- limit and autoretry mode in a fault condition. for a given set of conditions, the junction temperature of a power mosfet is given by equation 13: mosfet junction temperature, t j(max) (t a(max) + q ja ? p d ) (13) where p d = (i load ) 2 ? r ds(on) pcb layout techniques for optimal thermal management of power mosfet power dissipation help to keep device q ja as low as possible. see the section on pcb layout considerations for more information. v cc v out *user selected voltage clamp (a low bias current zener diode is recommended) 1n4688 (5v) 1n4692 (7v): logic-level mosfet 1n4695 (9v) 1n4702 (15v): standard-level mosfet 4230 f13 r sense r g 200 gate d1* d2* q1 figure 13. optional gate clamp for lower v gs(max) mosfets using staggered pin connectors the ltc4230 can be used on either a printed circuit board or on the backplane side of the connector, and examples for both are shown in figure 14. printed circuit board edge connectors with staggered pins are recommended as the insertion and removal of circuit boards do sequence the pin connections. supply voltage and ground connections on the printed circuit board should be wired to the edge connectors long pins or blades. control and status sig- nals (like reset n , fault and on) passing through the cards edge connector should be wired to short length pins or blades. applicatio s i for atio wu u u
25 ltc4230 4230f 4 3 2 1 + v cc n reset n sense n on r5 15k ltc4230* gate n fb n 4230 f14a 15 14 12 c timer 1 f gnd timer reset r4 36k v out 5v 5a q1 si4410dy r sense 0.007 c out r6 10k z1** z1: smaj10 *additional details omitted for clarity **optional r1 10 c1 0.1 f r2 10k v in 5v short long v cc reset long pcb edge connector (male) short backplane connector (female) 4 3 2 1 + v cc n sense n on r2 100k reset ltc4230* gate n fb n 4230 f14b 15 14 12 c timer 1 f r3 10k gnd timer reset n v out 5v 5a q1 si4410dy r sense 0.007 c out r1 36k r4 10k r5 10k pcb connection sense r x 10 c x 0.1 f z1** v cc 5v short long short pcb edge connector (male) long short backplane connector (female) q2 r7 15k z1: smaj10 *additional details omitted for clarity **optional (14a) hot swap controller on daughter board (14b) hot swap controller on backplane figure 14. staggered pin connections pcb connection sense there are a number of ways to use the ltc4230s on pin to detect whether the printed circuit board has been fully seated in the backplane before the ltc4230 commences a start-up cycle. the first example is shown in the schematic on the front page of this data sheet. in this case, the ltc4230 is mounted on the pcb and a 10k resistive divider is con- nected to the on pin. on the edge connector, r1 is wired to a short pin. until the connectors are fully mated, the on pin is held low, keeping the ltc4230 in an off state. once the connectors are mated, the resistive divider is con nected to v cc1 , v on > 1.314v and the ltc4230 begins a start-up cycle. in figure 14a, an ltc4230 is illustrated in a basic configu- ration on a pcb daughter card. the on pin is connected directly to v cc on the backplane once the card is seated into the backplane. r2 is provided to bleed off any potential static charge which might exist on the backplane, the connector or during card installation. a third example is shown in figure 14b where the ltc4230 is mounted on the backplane. in this example, a 2n2222 transistor and a pair of resistors (r4, r5) form the pcb connection sense circuit. with the card out of the chassis, q2s base is biased to v cc through r5, biasing q2 on and driving the ltc4230s on pin low. the base of q2 is also wired to a socket on the backplane connector. when a card is firmly seated into the backplane, the base of q2 is then grounded through a short pin connection on the card. q2 is biased off, the ltc4230s on pin is pulled-up to v cc and a start-up cycle begins. applicatio s i for atio wu u u
26 ltc4230 4230f in the previous three examples, the connection sense was hard wired with no processor (low) interrupt capability. as illustrated in figure 15, the addition of an inexpensive logic-level discrete mosfet and a couple of resistors offers processor interrupt control to the connection sense. r4 keeps the gate of m2 at v cc until the card is firmly mated to the backplane. a logic low for the on/off signal turns m2 off, allows the on pin to pull high and turns on the ltc4230. a more elaborate connection sense scheme is shown in figure 16. the bases of q1 and q2 are wired to short pins located on opposite ends of the edge connector because the installation/removal of printed circuit cards generally requires rocking the card back and forth. when v cc makes connection, the bases of transistors q1 and q2 are pulled high, biasing them on. when both are on, the ltc4230s on pin is held low, keeping the ltc4230 off. when the short base connector pins of q1 and q2 finally mate to the backplane, their bases are grounded, biasing the transistors off. the on pin is then pulled high by r3 enabling the ltc4230 and a power-up cycle begins. a software-initiated power-down cycle can be started by momentarily driving transistor m1 with a logic high signal. this in turn will drive the ltc4230s on pin low. if the on pin is held low for more than 8 m s, the ltc4230s gate n pin is switched to ground. applicatio s i for atio wu u u + 4 3 2 1 v cc n sense n ltc4230* 15 12 14 c load v out 5v 5a 4230 f15 r6 15k gate n gnd timer pcb connection sense c timer 1 f fb n on short long v cc 5v gnd on/off long z1: smaj10 m2: 2n7002lt1 *additional details omitted for clarity reset n r2 10k r4 10k m2 r1 10k r x 10 r sense 0.007 pcb edge connector (male) m1 si4410dy z1 r5 36k r7 10k p logic reset short c x 100nf backplane connector (female) figure 15. connection sense with on/off control + 4 3 2 1 v cc n sense n ltc4230* 15 12 14 c load v out 5v 5a 4230 f16 r5 15k gate n gnd timer pcb connection sense c timer 1 f fb n on long v cc gnd on/reset long z1: smaj10 m1: 2n7002lt1 q1, q2: mmbt3904lt1 *additional details omitted for clarity reset n m1 r x 10 r sense 0.007 pcb edge connector (male) m2 si4410dy z1 r3 10k r2 10k r1 10k r8 10k r4 36k r7 10k p logic reset short short last blade or pin on connector short c x 0.1 f backplane connector (female) q1 q2 last blade or pin on connector figure 16. connection sense for rocking the daughter board back and forth
27 ltc4230 4230f 4 3 2 1 10 a fb n r zx ltc4230* v cc n sense n v z (typ) = 26v r sense v cc > 15v 200 a 10 a charge pump r2 *additional details omitted for clarity 4230 f17 r1 v out logic figure 17. using an external resistor to limit zener current in high v cc applications figure 18. autoretry application high supply voltage operation considerations the ltc4230 can be used with supply voltages ranging from 1.7v to 16.5v. at high input supply voltages, the internal charge pump produces a minimum gate drive voltage of 7v for v cc > 15v. this minimum voltage drive is derived by an internal zener diode clamp circuit, as shown in figure 17. during pc board insertion or removal, sufficient transient current may flow through this zener diode. to limit the amount of current during transient events, an optional small resistor between the ltc4230s gate n pin and the gate of the external mosfet can be used, as shown in figure 17. a secondary benefit of this component is to minimize the possibility of high frequency parasitic oscillations in the power mosfet. applicatio s i for atio wu u u pcb edge connector (male) backplane connector (female) v cc1 3.3v long v cc2 2.5v long v cc3 1.8v long short r auto 1m fault gnd long r sense2 0.007 cx2 100nf cx1 100nf rx2 10 m2 irf7413 v cc1 gnd on fault 14 67 8 16171854 3 fb3 1 15 13 sense 1 gate 1 timer filter v cc2 sense 2 gate 2 sense 3 gate 3 v cc3 reset 3 2 r sense3 0.007 rx1 10 r8 5.1k r9 12k m3 irf7413 v out1 3.3v 5a v out2 2.5v 5a v out3 1.8v 5a r sense1 0.007 cx3 100nf rx3 10 c timer * 0.1 f c filter ** 15pf c auto 0.1 f m1 irf7413 z3 z2 z1 * system on time: 6.2ms **circuit breaker response time: 19.5 s z1, z2, z3: z1: smaj10 note: m1 mounted to 300mm copper area without c auto yields 8% and m1 case = 65 c with c auto = 0.1 f yields 4% and m1 case = 45 c reset 2 19 fb2 20 r7 10k reset 1 9 fb1 10 11 12 r10 11k r11 12k r6 10k r12 18k r13 12k 4230 f18 r5 10k master reset 3-input nor gate p or system logic c out3 c out2 c out1 ltc4230 + + +
28 ltc4230 4230f applicatio s i for atio wu u u autoretry after a fault to configure the ltc4230 to automatically retry after a fault condition, the fault (which has an internal 2 m a pull- up current source) and on pins can be connected to- gether, as shown in figure 18. in this case, the autoretry circuitry will attempt to restart the ltc4230 with an 7% duty cycle, as shown in the timing diagram of figure 19. to prevent overheating the external mosfet and other com- ponents during the autoretry sequence, adding a capacitor (c auto ) to the circuit introduces a delay at the on pin that adjusts the autoretry duty cycle. equation 14 gives the autoretry duty cycle, modified by the external time con- stant c auto : autoretry duty cycle = + t tt timer off timer 14 5 100 . % (14) where t timer = ltc4230 system time constant (see timer function) and t cv a off auto = m . 1 314 2 for the values shown, the external delay equals 65.7ms and the autoretry duty cycle drops from 7% to 4%. to increase the rc delay, the user may either increase c auto or r auto . overvoltage transient protection good engineering practice calls for bypassing the supply rail of any analog circuit. bypass capacitors are often placed at the supply connection of every active device, in addition to one or more large value bulk bypass capacitors per supply rail. if power is connected abruptly, the large bypass capacitors slow the rate of rise of the supply voltage and heavily damp any parasitic resonance of lead or pc track inductance working against the supply bypass capacitors. check for timer < 0.3v 1 3 7 6 5 8 4 first timing cycle 4230 f19 second timing cycle discharging mode normal mode check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 check for gate n < 0.25v fast comparator armed slow comparator armed once v filter > 1.26v, circuit breaker trips, all gate n pins pull low immediately 20 a pull-up 1.6 a pull-down 2 a pull-up v filter > 1.26v v ref 10 a pull-down load current < 150mv/r sense n 20 a pull-up 9 on/ timer gate n v out n i load n filter fault gate n v out n v sense n = 50mv regulated load current figure 19. autoretry timing
29 ltc4230 4230f figure 20. placing transient protection devices close to the ltc4230 + 4 3 2 1 v cc n sense n ltc4230* 12 14 c load n v out 4230 f20 15 r2 gate n gnd timer c timer fb n on on reset n 10 v in r sense 0.007 q n si4410dy r1 reset 0.1 f smaj10 *additional details omitted for clarity the opposite is true for ltc4230 hot swap circuits mounted on plug-in cards. in most cases, there is no supply bypass capacitor present on the powered supply voltage side of the mosfet switch. an abrupt connection, produced by inserting the board into a backplane connec- tor, results in a fast rising edge applied on the supply line of the ltc4230. since there is no bulk capacitance to damp the parasitic track inductance, supply voltage transients excite parasitic resonant circuits formed by the power mosfet capacitance and the combined parasitic inductance from the wiring harness, the backplane and the circuit board traces. these ringing transients appear as a fast edge on the input supply line, exhibiting a peak overshoot to 2.5 times the steady-state value. this peak is followed by a damped sinusoidal response whose duration and period are dependent on the resonant circuit parameters. since the absolute maximum supply voltage of the ltc4230 is 17v, transient protection against v cc > 16.8v supply voltage spikes and ringing is highly recommended. i n these applications, there are two methods for eliminat- ing these supply voltage transients: using zener diodes to clip the transient to a safe level and snubber networks. snubber networks are series rc networks whose time constants are experimentally determined based on the boards parasitic resonance circuits. as a starting point, the capacitors in these networks are chosen to be 10 to 100 the power mosfets c oss under bias. the series resistor is a value determined experimentally and ranges from 1 w to 50 w , depending on the parasitic resonance circuit. note that in all ltc4230 circuit schematics, transzorb ? diodes and snubber networks have been added to each 3.3v and 5v supply rail. these protection networks should be mounted very close to the ltc4230s supply voltage using short lead lengths to minimize lead inductance. this is shown schematically in figure 20, and a recommended layout of the transient protection devices around the ltc4230 is shown in figure 21. additional supply overvoltage detection/protection in addition to using external protection devices around the ltc4230 for large scale transient protection, low power zener diodes can be used with the ltc4230s filter pin to act as a supply overvoltage detection/protection circuit on either the high side (input) or low side (output) of the external pass transistor. recall that internal control cir- cuitry keeps the ltc4230 gate n voltage from ramping up if v filter > 1.26v, or when an external fault condition (v fault < 1.234v) causes fault to be asserted low. high side (input) overvoltage protection as shown in figure 22, a low power zener diode can be used to sense an overvoltage condition on the input (high) side of the main 5v supply. in this example, a low applicatio s i for atio wu u u v cc2 4230 f21 note: drawing is not to scale! use similar techniques for v cc1 and v cc3 *additional details omitted for clarity snubber network vias to gnd plane c x r x z 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 v cc2 on gnd ltc4230* figure 21. recommended layout for transient protection devices transzorb is a registered trademark of general instruments, gsi.
30 ltc4230 4230f applicatio s i for atio wu u u figure 22. ltc4230 high side overvoltage protection implementation pcb edge connector (male) backplane connector (female) v cc1 3.3v long v cc2 2.5v long v cc3 1.8v on/off long short fault gnd long short 10k r sense2 0.007 cx2 100nf cx1 100nf rx2 10 m2 irf7413 v cc1 gnd on fault ltc4230 14 fb3 1 15 13 sense 1 gate 1 filter timer v cc2 sense 2 gate 2 sense 3 gate 3 v cc3 reset 3 2 r sense3 0.007 rx1 10 r8 5.1k r9 12k m3 irf7413 v out1 3.3v 5a v out2 2.5v 5a v out3 1.8v 5a r sense1 0.007 cx3 100nf rx3 10 c filter 15pf c timer 0.1 f r4 10k optional v cc1 10k v cc1 r5 10k m4 v cc1 m1 irf7413 z3 v cc1 z2 z1 reset 2 19 fb2 20 r7 10k reset 1 9 fb1 10 r10 11k r11 12k r6 10k r12 18k r13 12k 4230 f22 r5 10k p or system logic master reset 3-input nor gate 67 816171854 3 12 11 c out3 c out2 c out1 v cc2 v cc3 6.2v z4 z5 z6 m4: 2n7002lt1 z1, z2, z3: smaj10 z4, z5, z6: 1n4691 note: for any v cc n > 7.7v, the ltc4230 is in overvoltage protection mode, fault is pulled low + + +
31 ltc4230 4230f applicatio s i for atio wu u u bias current 1n4691 zener diode is chosen to protect the system. here, the zener diode is connected from v cc to the ltc4230s filter pin. if the input voltage to the system is greater than 6.8v during start-up, the voltage on the filter pin is pulled higher than its 1.19v thresh- old. as a result, the gate n pin is not allowed to ramp and the second timing cycle will not commence until the supply overvoltage condition is removed. should the supply overvoltage condition occur during normal op- eration, internal control logic would trip the electronic circuit breaker and the gate would be pulled to ground, shutting off the external pass transistor. if a lower supply overvoltage threshold is desired, use a zener diode with a smaller breakdown voltage. a timing diagram for illustrating ltc4230 operation under a high side overvoltage condition is shown in figure 23. the start-up sequence in this case (between time points 1 and 2) is identical to any other start-up sequence under normal operating conditions. at time point 2, the input supply voltage causes the zener diode to conduct thereby forcing v filter > 1.19v. at time point 3, fault is asserted low and the timer pin voltage ramps down. at time point 4, the ltc4230 checks if v filter < 1.19v. fault is asserted low (but not latched) to indicate a start-up failure. only if the input overvoltage condition is removed before time point 5 does the start-up sequence resume at the second timing cycle. at this point in time, the gate n pin voltage is allowed to ramp up, fault is pulled to logic high and the circuit breaker is armed. should, at any time after time point 5, a supply overvoltage condition develop (v filter > 1.26v), the electronic circuit breaker will trip, the gate n will be pulled low to turn off the external mosfet and fault will be asserted low and latched. low side (output) overvoltage protection a zener diode can be used in a similar fashion to detect/ protect the system against a supply overvoltage condition on the load (or low) side of the pass transistor. in this case, the zener diode is connected from the load to the ltc4230s filter pin, as shown in figure 24. an additional diode, d1, prevents the filter pin from pulling low during output short-circuit. figure 25 illustrates the timing dia- gram for a low side output overvoltage condition. in this example, the ltc4230 can only sense the overvoltage supply condition after time point 5 and the gate n pin has ramped up to its nominal operating value. after time point 5, a supply voltage fault occurs at the load and the zener diode conducts, causing v filter to increase. at time point 6, v filter is greater than 1.26v, the circuit breaker trips, gate pulls to ground and fault asserts low and is latched. in either case, the ltc4230 can be configured to auto- matically initiate a start-up sequence. please refer to the section on autoretry after a fault for additional information. pcb layout considerations for proper operation of the ltc4230s circuit breaker function, a 4-wire kelvin connection to the sense resistors is highly recommended. a recommended pcb layout for the sense resistor, the power mosfet and the gate drive components around the ltc4230 is illustrated in fig- ure 26. in hot swap applications where load currents can reach 10a or more, narrow pcb tracks exhibit more resistance than wider tracks and operate at more elevated temperatures. since the sheet resistance of 1 ounce copper foil is approximately 0.54m w /square, track resis- tances add up quickly in high current applications. thus, to keep pcb track resistance and temperature rise to a minimum, pcb track width must be appropriately sized. consult appendix a of ltc application note 69 for details on sizing and calculating trace resistances as a function of copper thickness. in the majority of applications, it will be necessary to use plated-through vias to make circuit connections from component layers to power and ground layers internal to the pc board. for 1 ounce copper foil plating, a good starting point is 1a of dc current per via, making sure the via is properly dimensioned so that solder completely fills any void. for other plating thicknesses, check with your pcb fabrication facility.
32 ltc4230 4230f figure 23. high side overvoltage protection timing 1 3 7 6 5 4 4230 f23 fault is pulled low (but not latched), since the overvoltage happened before the end of the first timing cycle check for filter low (< v ref ) check for fault high (> v ref + 50mv) 2 fast comparator armed if the overvoltage goes away, the second cycle continues slow comparator armed filter < 1.19v on timer gate n v out n filter fault reset gate n v out n check for gate n < 0.25v power good applicatio s i for atio wu u u
33 ltc4230 4230f figure 24. ltc4230 low side overvoltage protection implementation applicatio s i for atio wu u u long long long short long short 10k r sense2 0.007 cx2 100nf cx1 100nf rx2 10 m2 irf7413 v cc1 gnd on fault ltc4230 14 fb3 1 15 13 sense 1 gate 1 filter timer v cc2 sense 2 gate 2 sense 3 gate 3 v cc3 reset 3 2 r sense3 0.007 rx1 10 r8 5.1k r9 12k m3 irf7413 v out1 3.3v 5a v out2 2.5v 5a v out3 1.8v 5a r sense1 0.007 cx3 100nf rx3 10 c filter 15pf c timer 0.1 f r4 10k optional v cc1 10k v cc1 r5 10k m4 v cc1 m1 irf7413 z3 v out1 z2 z1 reset 2 19 fb2 20 r7 10k reset 1 9 fb1 10 r10 11k r11 12k r6 10k r12 18k r13 12k 4230 f24 r5 10k p or system logic master reset 3-input nor gate 67 816171854 3 12 11 d1: 1n4148 m4: 2n7002lt1 z1, z2, z3: smaj10 z4, z5, z6: 1n4691 note: for any v out n > 8.4v, the ltc4230 is in overvoltage protection mode, fault is pulled low c out3 c out2 c out1 v out2 v out3 6.2v z4 z5 z6 d1 + + + pcb edge connector (male) backplane connector (female) v cc1 3.3v v cc2 2.5v v cc3 1.8v on/off fault gnd
34 ltc4230 4230f figure 25. low side overvoltage protection timing 1 3 7 6 5 4 4230 f24 check for filter low (< v ref ) check for fault high (> v ref + 50mv) 8 fast comparator armed 9 filter < 1.19v filter < 1.26v 1.234v on timer reset n gate n v out n filter fault check for timer < 0.3v 2 check for gate n < 0.25v applicatio s i for atio wu u u
35 ltc4230 4230f figure 26. recommended layout for ltc4230 r sense , power mosfet and feedback network 4230 f26 note: drawing is not to scale! use similar techniques for v cc1 and v cc2 **additional details omitted for clarity *optional components c timer c gx * via to gndplane r gx * 12k 5.1k 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 gnd timer ltc4230** fb3 reset 3 gate 3 sense 3 v cc3 d d d d g s s s power mosfet so-8 sense resistor (r sense ) current flow to load track width w w w current flow to load current flow to load w applicatio s i for atio wu u u appe dix u table 4 lists some current sense resistors that can be used with the circuit breaker. table 5 lists some power mosfets that are available. table 6 lists the web sites of several manufacturers. since this information is subject to change, please verify the part numbers with the manufacturer. table 4. sense resistor selection guide current limit value part number description manufacturer 1a lr120601r050 0.05 w 0.5w 1% resistor irc-tt 2a lr120601r025 0.025 w 0.5w 1% resistor irc-tt 2.5a lr120601r020 0.02 w 0.5w 1% resistor irc-tt 3.3a wsl2512r015f 0.015 w 1w 1% resistor vishay-dale 5a lr251201r010f 0.01 w 1.5w 1% resistor irc-tt 10a wsr2r005f 0.005 w 2w 1% resistor vishay-dale information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
36 ltc4230 4230f lt/tp 0702 2k ? printed in usa ? linear technology corporation 2001 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 l fax: (408) 434-0507 l www.linear.com related parts part number description comments ltc1421 2-channel hot swap controller 24-pin, operates from 3v to 12v and supports C 12v ltc1422 single channel hot swap controller in so-8 operates from 2.7v to 12v lt1641-1/lt1641-2 positive voltage hot swap controller operates from 9v to 80v ltc1642 single channel hot swap controller 16-pin, overvoltage protection to 33v ltc1644 pci hot swap controller 3.3v, 5v and 12v, 1v precharge, pci reset logic ltc1647 dual channel hot swap controller 8-pin, 16-pin, operates from 2.7v to 16.5v ltc4211 single hot swap controller with multifunction current control 2.5v to 16.5v, similar features as ltc4230 lt4250l/lt4250h negative voltage hot swap controllers in so-8 operates from C 20v to C80v, active current limiting ltc4251 C 48v hot swap controller in sot-23 C15v to C100v, active current limiting u package descriptio gn package 20-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) table 5. n-channel mosfet selection guide current level (a) part number description manufacturer 0 to 2 mmdf3n02hd dual n-channel so-8, r ds(on) = 0.09 w , c iss = 455pf on semiconductor 2 to 5 mmsf5n02hd single n-channel so-8, r ds(on) = 0.025 w , c iss = 1130pf on semiconductor 5 to 10 mtb50n06v single n-channel dd pak, r ds(on) = 0.028 w , c iss = 1570pf on semiconductor 10 to 20 mtb75n05hd single n-channel dd pak, r ds(on) = 0.0095 w , c iss = 2600pf on semiconductor table 6. manufacturers web sites manufacturer web site manufacturer web site temic semiconductor www.temic.com irc-tt www.irctt.com international rectifier www.irf.com vishay-dale www.vishay.com on semiconductor www.onsemi.com vishay-siliconix www.vishay.com intersil www.intersil.com diodes, inc. www.diodes.com appe dix u 0.337 ?0.344* (8.560 ?8.737) gn20 (ssop) 1098 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side 12 3 4 5 6 7 8910 0.229 ?0.244 (5.817 ?6.198) 0.150 ?0.157** (3.810 ?3.988) 16 17 18 19 20 15 14 13 12 11 0.016 ?0.050 (0.406 ?1.270) 0.015 0.004 (0.38 0.10) 45 0 ?8 typ 0.007 ?0.0098 (0.178 ?0.249) 0.053 ?0.068 (1.351 ?1.727) 0.008 ?0.012 (0.203 ?0.305) 0.004 ?0.0098 (0.102 ?0.249) 0.0250 (0.635) bsc 0.058 (1.473) ref

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